The invention is in the field of arithmetic operations performed by a digital computer and more particularly concerns detection of errors in add, subtract, multiply, divide, and square root operations performed by a digital computer.
In the prior art, means and techniques are provided for verifying the correctness of arithmetic and logical operation results. Apparatus are known for employing residue correlatives of the operands and results of add and subtract operations to check the veracity of the results. An apparatus is also taught in U.S. Pat. No. 3,227,865 for residue-based verification of a division operation.
However, the prior art does not include a single apparatus employing residue techniques to verify the outcomes of all of the arithmetic operations encountered in modern digital computing. In this regard, no single apparatus is known which can, based upon residues, check the results of add, subtract, multiply, divide, and root-taking operations.
Given the emphasis in modern computer design upon reduction of size and component count, it is manifest that manifold functionality for computer components is very desirable. In this vein, the inventor provides a single computer component with the ability to perform verification for the outcome of any one of these arithmetic operations.